Testing has emerged as a key constraint on the path to more advanced, reliable and cost effective semiconductor devices. Semiconductor process technology is characterized by Moore's Law, which states that the number of transistors in a given surface area will double every 18 months. This has enabled today's designers to pack high-volume production chips with 100 million transistors, straining test systems as more transistors and structures must be tested. This exponential growth rate requires continually increasing process, design and manufacturing complexities, which also drive the need for more test time and more comprehensive testing.
Currently, testing is performed in two basic configurations. Devices are either tested sequentially in a singular manner or several are tested at the same time in “parallel”. Singular tests are more common with complex products such as CPUs while memory devices are more often tested in parallel.
Productivity gains are often realized when testing (and probing) more than one device in parallel. Virtually all memory testing is done in parallel, where it is common to test 64 or 128 devices simultaneously, both at wafer-sort and at packaged unit class-test. The move to parallel test within other product categories such as microprocessors, RF and mixed signal is already underway and accelerating.
The probing requirements for parallel test at wafer-sort drive the need for more and more probe contacts on the sort probe card, across an increasing fraction of the wafer area. Some believe that ultimately contacting the entire wafer is expected to be the industry standard.
Generally speaking, the parallel testing of devices at wafer-sort involves interfacing a tester (being, for example, ATE—Automated Test Equipment) to a probe card which is adapted to simultaneously probe multiple devices. The application of the probe card to devices to be tested is by means of “touchdown”. A touchdown is typically an event where a probe card ‘touches’ with its needles the devices that are to be tested. Note that the probe card can support up to m tested devices (referred to also as m probe sites) simultaneously. Note also that the larger the value of m, the higher is the degree of parallelism. Note also that the term “probe sites” is not bound by any specific form of probe card and the means for contacting (e.g., touching) the probe to the device. Likewise this term is not bound by any form of touchdown and particularly not by the one described above.
In many cases, the computer-controlled equipment that tests electronic devices for functionality and performance is referred to as the ATE. The ATE includes control hardware, sensors, and software that perform testing and collect and analyze the test results. The ATE can support up to n test sites simultaneously. Each test site would typically contain a processing resource (one or more processors and associated m, the higher is the degree of parallelism. Note that the term “test sites” is not bound by any ATE and particularly not by ATE described above.
In order to increase parallelism: some constraints may apply:
1) The tester is adjusted and synchronized to utilize preferably maximum number of tester channels in parallel that are available to service the device I/Os,
2) The probe card is designed to meet the device specifications on one hand, and the parallelism specification on the other hand.
Note that in hitherto known testing methodologies, the parallelism of the tester and the probe card match, or, in other words m=n. Had this not been the case, the extra resources of the tester (in the case that n>m) or those of the probe card (in the case of m>n) would become redundant, since the number of the devices that can be tested in parallel is limited by the resources of the lesser of the two.
Each of the specified two requirements has a significant cost impact:
1) The tester cost soars with the increase in parallelism. As more devices are tested in parallel, more tester channels and power supplies are required, pushing up the hardware and other costs.
2) The cost of the probe card increases as the parallelism specification grows.
Nevertheless, parallel testing is eventually cheaper than singular testing, and more parallelism is in most cases cheaper than less parallelism. Increasing parallelism is a continuous effort in which all the factors are analyzed versus the current level of parallelism to determine the optimal ROI (Return On Investment) for a suggested parallelism increase.
The problem with existing parallel test methods is that the overall test time for a group of devices tested in parallel will be limited by the slowest tested device in the group. Probing cannot move on to the subsequent group of devices to be tested until all devices in the present touchdown are complete. Therefore, if one device takes 50% more test time than the remaining devices in the same touchdown, then the actual test time of all the devices (within the same touchdown) will be longer by 50%.
There is a need in the art to provide optimized parallel testing when the number of probe sites exceeds the number of test sites (m>n). There is still further need in the art to provide for a testing scheme in which the testing time of the slowest device will not prescribe the overall testing time.
There is still further need in the art to provide for a system and method facilitating parallel testing optimization using older generation ATE—Automatic Testing Equipment with later generation of probe card technology.